LTC2143CUP-14#PBF【PDF 20/38 页】IC ADC DUAL 14BIT 80 MSPS 64-QFN

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21454314fa

LTC2145-14/

LTC2144-14/LTC2143-14

allowed so the on-chip references can settle from the slight

temperature shift caused by the change in supply current

as the A/D leaves nap mode. Either channel 2 or both chan-

nels can be placed in nap mode; it is not possible to have

channel 1 in nap mode and channel 2 operating normally.

Sleep mode and nap mode are enabled by mode control

SDO (parallel programming mode).

DEVICE PROGRAMMING MODES

The operating modes of the LTC2145-14/LTC2144-14/

LTC2143-14 can be programmed by either a parallel in-

terface or a simple serial interface. The serial interface has

more flexibility and can program all available modes. The

parallel interface is more limited and can only program

some of the more commonly used modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to VDD. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to VDD or ground, or driven by 1.8V, 2.5V, or

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 2 shows the

modes set by CS, SCK, SDI and SDO.

Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)

PIN

DESCRIPTION

Clock Duty Cycle Stabilizer Control Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

SCK

Digital Output Mode Control Bit

0 = Full Rate CMOS Output Mode

1 = Double Data Rate LVDS Output Mode

(3.5mA LVDS Current, Internal Termination Off)

SDI/SDO Power Down Control Bit

00 = Normal Operation

01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode

10 = Channel 1 and Channel 2 in Nap Mode

11 = Sleep Mode (Entire Device Powered Down)

APPLICATIONS INFORMATION

Digital Output Test Patterns

To allow in-circuit testing of the digital interface to the

A/D, there are several test modes that force the A/D data

outputs (OF, D13-D0) to known values:

All 1s: All outputs are 1

All 0s: All outputs are 0

Alternating: Outputs change from all 1s to all 0s on

alternating samples.

Checkerboard: Outputs change from

101010101010101 to 010101010101010 on alternat-

ing samples.

The digital output test patterns are enabled by serially

programming mode control register A4. When enabled,

the Test Patterns override all other formatting modes: 2’s

complement, randomizer, alternate bit polarity.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A3. All digital outputs including

OF and CLKOUT are disabled. The high-impedance disabled

state is intended for in-circuit testing or long periods of

inactivity – it is too slow to multiplex a data bus between

multiple converters at full speed. When the outputs are

disabled both channels should be put into either sleep or

nap mode.

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire device is powered down,

resulting in 1mW power consumption. The amount of time

required to recover from sleep mode depends on the size

of the bypass capacitors on VREF, REFH, and REFL. For the

suggested values in Fig. 8, the A/D will stabilize after 2ms.

In nap mode the A/D core is powered down while the internal

reference circuits stay active, allowing faster wakeup than

from sleep mode. Recovering from nap mode requires at

least 100 clock cycles. If the application demands very

accurate DC settling then an additional 50μs should be

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